1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a semiconductor device having a circuit such as a command decoder that has the function of decoding command signals, which represent various kinds of commands, synchronously with an internal clock, and judging the states of the command signals.
In such a command decoder or the like, normally, states or patterns of various command signals are judged in order to produce a command judgment signal synchronous with an internal clock (normally referred to as a clocked judgment signal). The command judgment signals are output through command pins of an output port.
In recent years, dynamic random access memory (hereinafter abbreviated to DRAM) that is a semiconductor integrated circuit having a semiconductor device, which includes the command decoder or the like incorporated therein, has been required to exhibit a high processing speed.
However, for suppressing multi-signal selection, that is simultaneous selection of two or more than two clocked judgment signals to be output through command pins, the high processing speed exhibited by the SDRAM must be sacrificed. Otherwise, it becomes necessary to fully suppress a skew equivalent to a dispersion in timing between different command signals. The present invention relates to a means for coping with the multi-signal selection of clocked judgment signals and the skew between command signals while meeting the request for a higher processing speed to be exhibited by the DRAM.
2. Description of the Related Art
Normally, data is input as an external input signal to the DRAM. The input data is processed according to a clocked judgment signal produced by judging the states or patterns of command signals. Consequently, desired data is output. Especially, novel DRAMs including a synchronous DRAM (usually abbreviated to SDRAM) capable of transferring data at a high speed is designed to provide a data transfer speed corresponding to a frequency of, for example, 100 MHz or higher than 100 MHz. At this time, input or output of data and judgment of the states of the command signals must be carried out at a predetermined accurate phase relative to an externally supplied high-speed external clock. In other words, as far as the SDRAM is concerned, according to what timing a clocked judgment signal is output through a command pin of a command decoder or the like is important for outputting desired data quickly and stably.
Now, for a better understanding of problems on semiconductor integrated circuits including conventional semiconductor devices having the function of judging the states of command signals, the configuration and operations of conventional semiconductor devices will be described later with reference to FIG. 1 to FIG. 4 mentioned in xe2x80x9cBRIEF DESCRIPTION OF THE DRAWINGS.xe2x80x9d
A circuit block diagram showing the outline configuration of a first example of conventional semiconductor devices having the function of judging the states of command signals, is illustrated in FIG. 1. A conventional semiconductor device of the first example shown in FIG. 1 has a first current mirror circuit 310, a second current mirror circuit 320, and a third current mirror circuit 330. The first current mirror circuit 310, second current mirror circuit 320, and third current mirror circuit 330 amplify various command signals input through external control pins and thus determine the output levels of the command signals. The various command signals are, for example, a row address strobe /RAS, a column address strobe /CAS, and a write enabling signal /WE. Herein, the first to third current mirror circuits amplify the row address strobe /RAS, column address strobe /CAS, and write enabling signal /WE, thus producing command determination signals rasz, casz, and wez. The command determination signals rasz, casz, and wez are high (xe2x80x9cHxe2x80x9d: high voltage) or low (xe2x80x9cLxe2x80x9d: low voltage).
In FIG. 1, there are shown a first latch circuit 410, second latch circuit 420, and third latch circuit 430 for holding the command determination signals rasz, casz, and wez sent from the first to third current mirror circuits. The first to third latch circuits are each realized with a set-reset flip-flop (normally abbreviated to SFF). The first to third latch circuits latch information of command signals (that is, the command determination signals rasz, casz, and wez) synchronously with a clock (that is, an internal clock clkz). The clock is input via a current mirror circuit 500 for a clock through an external clock (CLK) input clock pin. The first to third latch circuits output command information latch signals rascz, cascz, and wecz that are in phase with the input command determination signals. The first to third latch circuits also output command information latch signals rascx, cascx, and wecx that are out of phase with the command determination signals. The current mirror circuit 500 for a clock functions as an input buffer for converting the level of the external clock CLK so as to produce an internal clock clkz.
Furthermore, in FIG. 1, there is shown a command decoder 100 for decoding the command information latch signals output from the first to third latch circuits. The command decoder 100 judges the states of the command signals including the row address strobe /RAS, column address strobe /CAS, and write enabling signal /WE. The command decoder 100 judges the states of the command signals from command information signals latched synchronously with the internal clock clkz by the first to third latch circuits. The states of the command signals indicate an operation to be performed by the SDRAM or the like. Moreover, the results of judgment made on the states of the command signals by the command decoder 100 are reported in the form of a xe2x80x9cHxe2x80x9d level (high-level) or xe2x80x9cLxe2x80x9d level (low-level) clocked judgment signal via an inverter through an associated node. The xe2x80x9cHxe2x80x9d level or xe2x80x9cLxe2x80x9d level clocked judgment signal is, for example, a clocked judgment signal AZ or BZ. The inverter is, for example, inverters 110 and 120. The node is, for example, a node n01 or n11.
The practical circuitry of the current mirror circuits, latch circuits, and command decoder will be described later in xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTS.xe2x80x9d
Referring to FIG. 2, the actions of a conventional semiconductor device of a second example of conventional semiconductor devices including the current mirror circuits, latch circuits, and command decoder will be clarified below. FIG. 2 shows the waveforms of input and output signals of components of the current mirror circuits, latch circuits, and command decoder. However, for brevity""s sake, the waveforms of the input and output signals of the first current mirror circuit 310 and second current mirror circuit 320 will be shown as representatives of those of the input and output signals of the plurality of current mirror circuits. Likewise, the waveforms of the input and output signals of the first latch circuit 410 and second latch circuit 420 will be shown as representatives of those of the input and output signals of the plurality of latch circuits.
Referring to FIG. 2, signals (the command determination signals rasz and casz in FIG. 2) are transmitted to the output stages of the first and second current mirror circuits 310 and 320. The signals are synchronous with and in phase with the row address strobe /RAS and column address strobe /CAS input through the external control pins. The internal clock clkz in phase with the clock CLK (that is, the external clock) input through the clock pin is transmitted to the output stage of the current mirror circuit 500 for a clock. In this case, the command determination signals rasz and casz and the internal clock clkz make a transition from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level or a transition from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level substantially simultaneously.
Data items (the command determination signals rasz and casz) output from the first and second current mirror circuits are determined by the first and second current mirrors 310 and 320. Thereafter, the states of the data items are latched synchronously with the internal clock clkz by the first and second latch circuits 410 and 420. The first and second latch circuits 410 and 420 output the command information latch signals rasca and casca (output signals outz2) as signals in phase with input signals inz (command determination signals rasz and casz). The first and second latch circuits 410 and 420 also output command information latch signals rascx and cascx (output signals outx2) as signals out of phase with the input signals inz.
Depending on the characteristics of the first latch circuit (or second latch circuit), the response speed exhibited by the semiconductor device when a signal inz output from the first latch circuit (or second latch circuit) makes a transition from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level may be different from the response speed exhibited when the signal inz makes a transition from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. Furthermore, it may take place that the output signal outz2 in phase with the input signal inz and the output signal outx2 out of phase therewith do not make a transition simultaneously. One of the reasons lies in that the response speed of an n-channel MOS transistor (NMOS transistor) is much higher than that of a p-channel MOS transistor (PMOS transistor). The NMOS transistor is actuated when an input signal makes a transition from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, while the PMOS transistor is actuated when the input signal makes a transition from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level. In the conventional semiconductor device of the first example, when the input signal inz changes from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level (that is, changes from an unselected state to a selected state), the output signals outz2 and outx2 are output relatively quickly. When the input signal changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level (that is, changes from the selected state to the unselected state), the output signals outz2 and outx2 are output relatively slowly. This case will be described as an example.
Under the above conditions, an attempt is made to judge the states of command signals in consideration of the logic of simple decoding performed by the command decoder 100. The attempt would be discouraged because when a selected signal is driven to an unselected state, an event of multi-signal selection may occur due to a skew between the command signals. For preventing the multi-signal selection, a duty ratio of the conventional semiconductor device of the first example (that is, the drivability of a circuit) is lowered for driving an unselected signal to a selected state. This causes the semiconductor device to exhibit a relatively low response speed. The duty ratio of the semiconductor device is raised for driving a selected signal to the unselected state so that the semiconductor device will exhibit a relatively high response speed. The dimensions of the command decoder 100 are set according to the duty ratio of the semiconductor device.
The clocked judgment signals AZ and BZ to be output from the command decoder 100 are command judgment signals that become xe2x80x9cHxe2x80x9d when selected. When the signals input to the command decoder 100 are all driven to become xe2x80x9cHxe2x80x9d, an output signal become xe2x80x9cHxe2x80x9d to be selected.
To be more specific, the duty ratio of the semiconductor device for driving a PMOS transistor included in a NAND circuit on the first stage of the command decoder 100 is made much higher than that for driving an NMOS transistor. The reverse is true of an inverter on the output stage of the command decoder 100. As is apparent from the waveforms of signals shown in FIG. 2, an input node n01 (or node n11) of an inverter 110 (or inverter 120) on the output stage is likely to become xe2x80x9cHxe2x80x9d high. In contrast, an output node thereof is likely to become xe2x80x9cLxe2x80x9d. Thus, the dimensions of the command decoder 100 are determined so that the semiconductor device will exhibit a high response speed when driving a selected signal to an unselected state.
In the conventional semiconductor device of the first example, as shown in FIG. 2, the command information latch signal rascz and command information latch signal cascx become xe2x80x9cHxe2x80x9d, and the node n01 becomes xe2x80x9cLxe2x80x9d. The clocked judgment signal AZ is therefore selected and a desired action is performed. However, the logical states of the command information latch signals rascz and cascz are about to be selected because of a skew. The node n11 is therefore going to be driven to become xe2x80x9cLxe2x80x9d. Owing to the foregoing dimensions, the clocked judgment signal BZ will not be selected. The semiconductor device will act normally.
FIG. 3 is a circuit block diagram showing the outline configuration of a semiconductor device of the second example of conventional semiconductor devices having the function of judging the states of command signals. The conventional semiconductor device of the second example shown in FIG. 3 has, in addition to the current mirror circuits, latch circuits, and command decoder included in the first example, a dummy latch circuit 600. The dummy latch circuit 600 monitors the latest action of a latch circuit. In the conventional semiconductor device of the second example, a dummy latch signal dsffz is produced by the dummy latch circuit 600. The dummy latch signal dsffz is supplied simultaneously to a first latch circuit 440, a second latch circuit 450, and a third latch circuit 460 respectively. This is intended to make the transition timing of output signals of the latch circuits mutually consistent, and to eventually overcome a skew. The practical circuitry of the dummy latch circuit and latch circuits will be described later in xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTS.xe2x80x9d
In this case, the configuration of the first to third current mirror circuits 310 to 330 and that of the command decoder 100 are identical to those in the first example. The description of the first to third current mirror circuits and command decoder will be omitted.
The dummy latch circuit 600 in FIG. 3 fixes the input signal inz, which is input to a normally employed latch circuit, at xe2x80x9cLxe2x80x9d level. An output signal of the dummy latch circuit 600 (that is, the dummy latch signal dsffz) is pulsed. The response speed of the conventional semiconductor device of the second example is the lowest when an input signal is xe2x80x9cLxe2x80x9d. When the dummy latch circuit produces a pulsed output signal, all the SFFs are supposed to have completed data latching. If each latch circuit produces the output signals outz2 according to the timing that the pulsed output signal is produced, the foregoing operations will be performed.
To be more specific, the conventional semiconductor device of the second example shown in FIG. 3 has a transfer gate connected to the output node of each latch circuit. The transfer gate is turned on or off using the dummy latch signal dsffz that is an output signal of the dummy latch circuit. When the dummy latch signal dsffz is output, the state of each control pin is latched at two output nodes a and b of each latch circuit. When the action of an inverter is counted as one step and an action of turning on the transfer gate is counted as one step, outputs of each latch circuit are produced after a logical delay of two steps.
For making clear the operations of the conventional semiconductor device of the second example, FIG. 4 shows the waveforms of input and output signals of the current mirror circuits, dummy latch circuit, latch circuits, and command decoder. However, for brevity""s sake, the waveforms of input and output signals of the first current mirror circuit 310 and second current mirror circuit 320 will be shown as representatives of those of the plurality of current mirror circuits. The waveforms of input and output signals of the first latch circuit 440 and second latch circuit 450 will be shown as representatives of those of the plurality of latch circuits.
Referring to FIG. 4, similarly to FIG. 2, signals (command determination signals rasz and casz shown in FIG. 3) are transmitted to the output stages of the first and second current mirror circuits 310 and 320. The signals are synchronous with, and in phase with, a row address strobe /RAS and column address strobe /CAS which are input through external control pins. An internal clock clkz in phase with a clock CLK input through a clock pin is transmitted to the output stage of the current mirror circuit 500 for a clock. In this case, the command determination signals rasz and casz and the internal clock clkz make a transition fromxe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level or a transition from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level substantially simultaneously.
As is apparent from FIG. 4, the dummy latch signal dsffz is produced according to the timing that the logical state of either the output node a or b of each latch circuit is determined last. Two steps of actions made until the transfer gate of each latch circuit is turned on with the dummy latch signal dsffz are regarded as a margin in timing of actuating the semiconductor device. The levels of the output signals of each latch circuit, for example, the command information latch signals rascz and rascx or cascz and cascx, are varied simultaneously.
Furthermore, referring to FIG. 4, similarly to FIG. 2, the command information latch signals rascz and cascx are driven to become xe2x80x9cHxe2x80x9d and the node n01 is driven to become xe2x80x9cLxe2x80x9d. Consequently, the clocked judgment signal AZ is selected. However, in this case, the logical states of the command information latch signals rascz and cascz are about to be selected because of a skew. The node n11 is going to be driven to become xe2x80x9cLxe2x80x9d. Owing to the aforesaid dimensions, the clocked judgment signal BZ will not be selected, and the semiconductor device will operate normally.
The use of the dummy latch signal dsffz will presumably lead to a considerably reduced risk of multi-signal selection of command signals caused by a skew. The dimensions of the command decoder must be, similarly to that in the first example, set according to the duty ratio of the semiconductor device. That is to say, the duty ratio of the semiconductor device is lowered for driving an unselected signal to a selected state. The duty ratio thereof is raised for driving a selected signal to an unselected state. One of the reasons will be described. Namely, when the duty ratio of the semiconductor device for driving an unselected output signal to the selected state is high, multi-signal selection may-occur because input signals are all synchronous with one another.
As mentioned above, in either of the conventional semiconductor devices shown in FIG. 1 and FIG. 3, the dimensions of the command decoder must be adjusted to prevent the occurrence of multi-signal selection of command signals due to a skew. Moreover, the adjustment must be made according to the duty ratio of the semiconductor device. Namely, the duty ratio of the semiconductor device is lowered for driving an unselected signal to the selected state. The duty ratio thereof is raised for driving a selected signal to the unselected state.
However, even when the dimensions of the command decoder are adjusted as mentioned above, it is hard to perfectly prevent multi-signal selection stemming from a skew. Moreover, in the conventional semiconductor devices, the dimensions of the command decoder are adjusted at the sacrifice of the high processing speed of an SDRAM or the like. The SDRAM or the like performs a desired operation in this state. This poses a problem in that the request for the high processing speed of the SDRAM or the like cannot be met fully. Consequently, a margin in timing of accessing or actuating a semiconductor device decreases. This may become a bottleneck in developing high-speed devices.
The present invention attempts to solve the foregoing problems. An object of the present invention is to provide a semiconductor integrated circuit having a semiconductor device capable of preventing occurrence of multi-signal selection of command signals due to a skew when judging the states of various command signals, and making it possible to perform operations at a high speed.
To accomplish the above object, according to the present invention, a semiconductor integrated circuit having a semiconductor device has a command decoder unit for decoding command signals synchronously with an internal clock. An internal signal whose timing of the internal signal precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit.
Preferably, in the semiconductor integrated circuit of the present invention, a signal produced by a delayed lock loop (DLL) is used as the internal signal.
Moreover, according to the present invention, the semiconductor integrated circuit has a command decoder unit for decoding command signals synchronously with an external clock. A first internal signal whose timing precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit. A second internal signal produced after the states of the command signals to be input to the command decoder unit are determined is used to activate the command decoder.
Preferably, a signal produced by a DLL is used as the first internal signal.
More preferably, a signal produced by a dummy latch circuit for monitoring the last operation of a command signal hold circuit for holding the states of the command signals, is used as the second internal signal.
Furthermore, according to the first aspect of the present invention, a semiconductor integrated circuit having a semiconductor device comprises a command decoder unit for decoding command signals synchronously with an external clock; and a command decoder control unit for producing a command decoder control signal used to reset the command decoder unit in response to an internal signal whose timing precedes the timing of the command decoder unit decoding the command signals, for driving the command decoder control signal to the first state, and for supplying the command decoder control signal to the command decoder unit.
Preferably, the duty ratio of the semiconductor integrated circuit may be such that the semiconductor integrated circuit exhibits a high response speed when driving an unselected transistor that is a component of the command decoder unit to a selected state, and exhibits a low response speed when-driving a selected transistor to an unselected state. Nevertheless, it is possible to prevent two or more than two command signals being selected simultaneously because of inconsistency in timing of the command signals. Moreover, the operations can be performed at a high speed.
Furthermore, according to the second aspect of the present invention, a semiconductor integrated circuit having a semiconductor device comprises a command decoder unit for decoding command signals synchronously with an external clock; and a command decoder control unit for producing a command decoder control signal used to reset the command decoder unit in response to a first internal signal whose timing precedes the timing of the command decoder unit decoding the command signals, for driving the command decoder control signal to the first state, and for supplying the command decoder control signal to the command decoder. The command decoder control signal is used to reset the command decoder unit. Thereafter, when a second internal signal is used to activate the command decoder, the command decoder control signal is changed from the first state to the second state. The second internal signal is produced after the states of the command signals to be input to the command decoder unit are determined.
Preferably, according to the second aspect, similarly to the first aspect, the duty ratio of the semiconductor integrated circuit may be such that the semiconductor integrated circuit exhibits a high response speed when driving an unselected transistor that is a component of the command decoder unit to a selected state, and exhibits a low response speed when driving a selected transistor to an unselected state. Nevertheless, it is possible to prevent two or more than two command signals being selected simultaneously because of inconsistency in timing of the command signals. Besides, operations can be performed at a high speed.
In short, in the semiconductor integrated circuit having the semiconductor device of the present invention, an internal signal is used to inactivate (reset) a command decoder unit. The internal signal is produced by a DLL or the like, and leading command signals that are input through external control pins and then held. In other words, the timing of the internal signal precedes the timing of the command decoder unit judging the logical state of each command pin. Furthermore, after the internal signal is used to inactivate the command decoder unit and the information of each command pin is determined, the command decoder unit is activated in order to judge the states of various command signals. There is no fear that two or more than two command signals may be selected simultaneously because of a skew between the command signals.
According to the present invention, when the states of various command signals are judged, the occurrence of multi-signal selection of command signals stemming from a skew can be prevented perfectly. Furthermore, according to the present invention, the dimensions of the command decoder unit need not be adjusted in consideration of the adverse effect of a skew between command signals. High-speed operations can be realized for an SDRAM or the like.